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Josephson Junction Optimization

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  • Team Members :John Mark Kreikebaum, Larry Chen
  • Collaborators :Kevin O’Brien
  • Start Date :October 2017
  • Status :Stable process developed, but there’s always room for improvement
  • Presentations :2020 APS March Meeting (link)

Project Description

Josephson junctions, fabricated by isolating two superconductors with a thin insulating barrier, are the core circuit element for superconducting solid state quantum coherent devices. The non-linear inductance from this structure can be used in a variety of ways, notably in transmons where the junction is shunted with a large capacitance to form an anharmonic oscillator with individually addressable energy levels [1].

Precise control over junction properties is crucial for state-of-the-art devices such as: quantum processors utilizing the cross-resonance gate [2], single microwave photon detectors based on ensembles of identical qubits [3], and traveling wave amplifiers where variations in nominally identical junctions lead to unwanted impedance variations [4]. Therefore, we focus on improving the reproducibility of shadow-evaporated sub-micron Al/AlOx/Al Josephson junctions common to nearly all current qubits [5].

The critical current, Ic, of a Josephson junction, inversely proportional to its inductance, is tuned by either varying the critical current density, Jc, or the junction area. The former involves modifying the tunnel barrier thickness via the oxidation time or pressure when using a thermally grown barrier. After fabrication, junctions can be automatically probed to measure their room temperature resistance from which Ic can be inferred using the Ambegaokar-Baratoff formula [6].

Our wafer-scale fabrication process produces 64, 1x1 cm dies from a 150 mm wafer with junctions located within the central ~ 50 sq. cm of the die array. Thus high uniformity is desired over this length scale. Furthermore, in order to reduce susceptibility to flux noise in tunable circuits, we also fabricate asymmetric SQUIDs [1, 7], where it is important to push the limits of how small a junction can be made without sacrificing yield.

[1] Charge-insensitive qubit design derived from the Cooper pair box
[2] Operation and intrinsic error budget of a two-qubit cross-resonance gate
[3] Itinerant Microwave Photon Detector
[4] A near–quantum-limited Josephson traveling-wave parametric amplifier
[5] A quantum engineer's guide to superconducting qubits
[6] Tunneling Between Superconductors
[7] Tunable Superconducting Qubits with Flux-Independent Coherence

What we did

We performed a systematic study to determine which process variables can be adjusted to improve junction uniformity and yield. So far, more than 45 wafers have been made and over 100,000 junctions have been probed. We exposed bridge-free “Manhattan Style” junctions with a Raith EBPG 5150.
  • Ultrasonic development:Ultrasonically assisted development helps remove developed resist through high aspect ratio resist channels, significantly reducing clogs which lead to open circuits.
  • Oxygen plasma “ashing” uniformity: Used as a gentle post-develop, pre-evaporation, clean of the substrate, oxygen plasma cleaning has numerous effects on the resulting junction, so it must be very uniform site to site
  • Dynamic oxidation:Instead of charging the oxidation chamber to a set pressure and waiting, improvements in uniformity were found by continuously flowing oxygen during the oxidation.
  • Low evaporation rates:Since the tunnel barrier thickness is not uniform grain to grain or at grain boundaries, we explored lower energy depositions to form smaller grains. We hypothesize this led to improved uniformity because the effective barrier thickness becomes more uniform site to site when there are more grains per junction.
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Current Status & Next Steps

The current process can produce junction test wafers with 100% junction yield (N=3000). Probing each junction, we find a relative standard deviation (RSD) in Ic of 3.5% for single junctions and 3.8% for 6:1 asymmetric SQUIDs across areas of 50 sq. cm. Looking within a 1 sq. cm moving window across the wafer to gauge the expected variation within a given chip, we find an average RSD of 1.3% with some areas as low as 0.7%. A fixed-frequency qubit sample made with this process exhibited T1’s and T2echo’s over 100 us, indicating that the process variables modified to improve uniformity did not come at the expense of qubit coherence.

Looking forward, the new ashing process can likely be further optimized and location specific corrections should be made to junction areas to correct for evaporator geometry imposed uniformity limitations.

Relevant Publications :

Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits, Fabrication of stable and reproducible submicron tunnel junctions, The atomic details of the interfacial interaction between the bottom electrode of Al/AlOx/Al Josephson junctions and HF-treated Si substrates,