3D Integration

Certified Company ISO 9001-2008
  • Team Members: Jie “Roger” Luo, Brian Marinelli, Kyunghoon Lee
  • Collaborators :William Oliver (Lincoln Labs)
  • Start Date: September 2019
  • Status :In Progress

Project Description

Even within the field of superconducting qubits there are a wide variety of quantum processor architectures. Materials, processor layouts, and qubit type are some important ways in which quantum processors (QPUs) differ from one another. In recent years there has been a growing interest in also changing the processor dimensionality, finding creative ways to integrate low-loss three-dimensional structures into formerly planar devices. The goal is to employ these methods of 3D integration to scale up quantum processors for NISQ applications, by overcoming the major scalability limitations that are faced by the current state of the art 2D devices.

We are working towards the design and fabrication of a scalable 3D integrated QPU. Our project has four main stages: design and simulation to understand the benefits of 3D integration as well as any new problems it may present, development of the fabrication methods necessary for 3D integration, testing of 3D integrated QPUs to compare the performance and capabilities to existing 2D processors, and employing these devices and the benefits they offer to perform interesting experiments and quantum simulations.

What we did

Currently we are focused on developing quantum-grade low-loss flip-chip technology for use with superconducting quantum circuits. Flip-chip refers to a technique of bonding two silicon chips (in our case using Indium bump bonding) so that the circuitry on one chip can be connected to and interact with circuit elements on the other chip. The conventional micro-electronics industry has been employing various traditional flip-chip architectures for decades in mass production. It has proven to be a successful way of combining sophisticated chips optimized for different functionalities together for complicated sensing and computing. However, those techniques were not quantum-grade and our R&D goal is to create a technology that elegantly combines the quantum chips in a low-loss way with diminishing cross-talks. From extensive simulation of the electromagnetic environment of a flip-chip device we have been able to draw some important conclusions about the benefits it offers:

  • 1. Significant crosstalk reduction between circuit elements located on different chips and not directly facing each other

  • 2. Field confinement of resonator and transmission line modes in the lateral dimensions further reduces crosstalk between elements and essentially eliminates crosstalk between circuit elements located on different chips and not directly facing each other.

  • 3. Slot line mode radiation losses are eliminated by direct galvanic connections between pieces of ground plane around active elements.

Simulation has allowed us to develop general guidelines about processor design and layout, which we have used to inform our design of a flip-chip QPU. In the design process we have also benefited from greater flexibility in control line routing and placement of tuning and coupling elements, made possible by the flip chip architecture. We have finalized the design of our first-generation flip-chip QPU and fabrication is in progress. Once fabricated, it will allow us to benchmark 3D QPU performance against current 2D devices and provide insights into how we can improve device performance in future iterations.

In parallel with the process of design and simulation we have made significant progress in developing our own fabrication methods for realizing a flip chip QPU. We have developed recipes for patterning and depositing the thick (>3μm) structures required and a technique for lithographically defined air-bridges which ensure good grounding across extended structures and further crosstalk mitigation.


Current Status & Next Steps

Currently we are pursuing three major activities towards completing the stages of our project. First, we are working to finish developing our own processes so that we can perform all steps in the 3D QPU fabrication. Next, once fabrication of our first 3D QPU is complete we will perform extensive device characterization and benchmarking, with a focus on understanding how 3D integration is improving or limiting device performance, allowing us to fine tune our design guidelines for future QPUs. Lastly, now that our first-generation designs have been finalized, we have a clearer understanding of the parameter regimes of the device. This has allowed us to begin exploring and designing experiments most well-suited to take advantage of the unique benefits of our QPU including all-to-all qubit connectivity and a broad range of available interaction strengths.

In a parallel thrust we are also considering other useful applications of the 3D architectures we are developing. For example, we are exploring high impedance linear inductors made using flip-chip technology.

Relevant Publications

Rosenberg, D., Kim, D., Das, R. et al. 3D integrated superconducting qubits. npj Quantum Inf 3, 42 (2017). https://doi.org/10.1038/s41534-017-0044-0,

B Foxen, et al. (2017). Qubit compatible superconducting interconnects Quantum Science and Technology, 3(1), 014005,

arXiv:1912.10942v2 [quant-ph]